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| CXP83200A CMOS 8-bit Single Chip Microcomputer Description The CXP83200A is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP83120A/83124A and CXP83232/83240. Piggyback/ evaluator type 100 pin PQFP (Ceramic) Features * Wide-range instruction system (213 instructions) to LQFP supported QFP supported cover various types of data - 16-bit operation/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 400ns at 10MHz operation 8s at 500kHz operation 122s at 32kHz operation * Applicable EPROM LCC type 27C512 (Maximum 40K bytes are available.) * Incorporated RAM capacity 1120 bytes (Including LCD display data area) * Peripheral functions - A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32s/10 MHz) - Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel - Timer 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter 32kHz timer/counter - LCD controller/driver Maximum 160 segment display possible (for 1/4 duty) 4 lines for common output, 40 lines for segment output Display method static: 1/2, 1/3, 1/4 duty Bias method: 1/2, 1/3 bias - Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO - PWM output 14 bits, 1 channel * Interruption 15 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP83200A. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E94831A68-PS CXP83200A Pin Configuration in Piggyback Mode (QFP package) PE1/INT1/EC1 PE0/INT0/EC0 SEG39/PG7 SEG38/PG6 SEG37/PG5 SEG36/PG4 SEG35/PG3 SEG34/PG2 SEG33/PG1 SEG32/PG0 TEX Vss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/PWM PE6/TO/ADJ PB0/CINT PB1/ CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PA0/AN0 1 2 3 4 5 6 7 80 79 78 77 76 75 74 SEG26/PF2 SEG25/PF1 SEG24/PF0 SEG23/PD7 SEG22/PD6 SEG21/PD5 SEG20/PD4 SEG19/PD3 SEG18/PD2 SEG17/PD1 SEG16/PD0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 TX NC VDD A12 A15 9 10 11 12 13 14 15 16 17 18 19 20 21 4 A6 A5 A4 A3 A2 A1 A0 NC D0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE D7 D6 A7 NC 8 A14 VDD A13 SEG31/PF7 SEG30/PF6 SEG29/PF5 SEG28/PF4 SEG27/PF3 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND NC D1 D2 D3 D4 D5 22 EXTAL2 XTAL2 Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 91) are both connected to GND. -2- PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 EXTAL1 XTAL1 COM0 AVREF AVss VLC3 VLC2 VLC1 RST Vss VL CXP83200A Pin Configuration in Piggyback Mode (LQFP package) PE3/INT3/NMI PE1/INT1/EC1 PE0/INT0/EC0 SEG39/PG7 SEG38/PG6 SEG37/PG5 SEG36/PG4 SEG35/PG3 SEG34/PG2 SEG33/PG1 SEG32/PG0 PE2/INT2 TEX Vss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PE4/RMC PE5/PWM PE6/TO/ADJ PB0/CINT PB1/CSO PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 PH3 PH4 PH5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 OE A10 CE D7 D6 D5 D4 D3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG23/PD7 SEG22/PD6 SEG21/PD5 SEG20/PD4 SEG19/PD3 SEG18/PD2 SEG17/PD1 SEG16/PD0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 TX NC VDD SEG31/PF7 SEG30/PF6 SEG29/PF5 SEG28/PF4 SEG27/PF3 SEG26/PF2 SEG25/PF1 COM1 EXTAL2 Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 89) are both connected to GND. -3- PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 EXTAL1 XTAL1 XTAL2 COM0 COM2 AVREF AVss VLC3 VLC2 VLC1 RST PH6 PH7 Vss VL SEG24/PF0 CXP83200A Pin Configuration in Evaluator Mode (QFP package) PE1/INT1/EC1 PE0/INT0/EC0 SEG39/PG7 SEG38/PG6 SEG37/PG5 SEG36/PG4 SEG35/PG3 SEG34/PG2 SEG33/PG1 SEG32/PG0 TEX Vss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/PWM PE6/TO/ADJ PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PA0/AN0 1 2 3 4 5 6 80 79 78 77 76 75 SEG26/PF2 SEG25/PF1 SEG24/PF0 SEG23/PD7 SEG22/PD6 SEG21/PD5 SEG20/PD4 SEG19/PD3 SEG18/PD2 SEG17/PD1 SEG16/PD0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 A7/D7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 TX NC VDD SEG31/PF7 SEG30/PF6 SEG29/PF5 SEG28/PF4 VLC1 SEG27/PF3 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A12 A15 NC 4 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 NC RD 5 6 7 8 9 10 11 12 13 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC HALT A10 E/P I/T MON 14 15 16 17 18 19 20 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SYNC GND RST WR NC C2 C1 22 A14 VDD A13 EXTAL2 XTAL2 Note) 1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 91) are both connected to GND. -4- PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 EXTAL1 XTAL1 COM0 AVREF AVss VLC3 VLC2 RST Vss VL CXP83200A Pin Configuration in Evaluator Mode (LQFP package) PE3/INT3/NMI PE1/INT1/EC1 PE0/INT0/EC0 SEG39/PG7 SEG38/PG6 SEG37/PG5 SEG36/PG4 SEG35/PG3 SEG34/PG2 SEG33/PG1 SEG32/PG0 PE2/INT2 TEX Vss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PE4/RMC PE5/PWM PE6/TO/ADJ PB0/CINT PB1/CSO PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2 PH3 PH4 PH5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A15 A12 A7/D7 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 RD WR SYNC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD A14 A13 A8 A9 A11 HALT A10 E/P I/T MON RST C1 C2 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG23/PD7 SEG22/PD6 SEG21/PD5 SEG20/PD4 SEG19/PD3 SEG18/PD2 SEG17/PD1 SEG16/PD0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 TX NC VDD SEG31/PF7 SEG30/PF6 SEG29/PF5 SEG28/PF4 SEG27/PF3 SEG26/PF2 SEG25/PF1 COM1 EXTAL2 Note) 1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 89) are both connected to GND. -5- PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 EXTAL1 XTAL1 XTAL2 COM0 COM2 AVss AVREF VLC3 VLC2 VLC1 RST PH6 PH7 Vss VL SEG24/PF0 CXP83200A EPROM Read Timing (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Address Data input delay time Address Data Hold time Symbol Pins A0 to A15 D0 to D7 A0 to A15 D0 to D7 0 Min. Max. 120 Unit ns ns tACC tIH 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D7 Products List Products Option item Mask type CXP83120A CXP83124A CXP83232A CXP83240A Package Rom capacitance RAM capacitance Pull-up resistance for reset 20K bytes 100-pin plastic QFP/LQFP 24K bytes 32K bytes 40K bytes Piggyback/evaluator type CXP83200A-U01Q CXP83200A-U01R 100-pin ceramic PQFP EPROM 40K bytes 1120 bytes Existent 644 bytes 1120bytes Existent/Non-existent -6- CXP83200A Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggyback/evaluator product Evaluator mode Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU Probe (27C512 only) EPROM adaptor Pin 1 marking Note) Evaluation cap should be connect to CPU probe. Pin 1 index CPU probe for LQFP -7- CXP83200A Package Outline Unit: mm 100PIN PQFP (CERAMIC) PIN NO. 1 INDEX INDEX 100 18.7 16.3 0.2 81 81 100 PIN No. 1 INDEX 1 80 80 1 0.65 0.05 4.5 1.27 0.13 22.3 0.25 18.12 0.2 12.02 14.22 24.7 6.0 0.3 1.0 0.7 30 51 51 30 31 9.48 11.66 15.58 0.2 50 1.3 0.3 50 0.45 31 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE PQFP-100C-L01 AQFP100-C-0000-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT CERAMIC GOLD PLATING 42 ALLOY 5.7g 3.57 0.36 JEDEC CODE + 0.05 0.15 - 0.02 0.50 0.25 100PIN PQFP (CERAMIC) 16.0 0.4 14.0 0.2 75 76 0.5 0.05 51 12.4 50 0.5 0.05 3.2 0.2 1.5 0.8 0.2 26 10.44 MAX 0.3 0.08 + 0.08 0.18 - 0.03 INDEX 12.0 0.15 + 0.08 0.18 - 0.03 100 1 INDEX 12.8 0.2 25 PACKAGE STRUCTURE PACKAGE MATERIAL CERAMIC GOLD PLATING 42 ALLOY 2.2g + 0.05 0.127 - 0.02 + 0.15 0.2 - 0.13 6.9 SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L02 AQFP100-C-1414-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 3.32 -8- 12.0 0.15 |
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